1. Field of the Invention
The present invention relates to a terminal adapter for broad band integrated services digital network, and more particularly to a terminal adapter which is applicable to the both of variable bit rate ATM(Asynchronous Transfer Mode) cell and constant bit rate ATM cell.
In ISDN, all communication data is digitalized and transmitted and received via high speed single communication network. In prior communication system, separate communication network is necessary for each communication system such as telephone or computer etc. On the contrary, ISDN use a high speed single digital communication network for whole services.
BISDN is ISDN which is extended to broad band signal based on the technique of the ISDN. In BISDN, both narrow band signal such as telephone, facsimile and internet service and broad band signal of video signal such as image conference and video telephone are included.
ATM is known as a effective mode by which the above variable services of BISDN are accomplished. In ATM, service information is transmitted by stream of a constant sized packet called ATM cell. The ATM cell is 53 bytes, which consist of 5 byte-cell header and 48 payload. ATM uses defined protocol standard to transmit service information systematically. In the defined protocol standard, the cell header is processed by ATM layer and the user information section by ATM adaptation Layer(AAL).
Terminal adapter for BISDN is apparatus which connects ATM network to a conventional communication devices such as modem, telephone or facsimile, more specifically connects SB point of ATM network to R point of the conventional communication devices.
2. Description of the Prior Art
FIG. 1 is a block diagram illustrating a terminal adapter for BISDN in the prior art.
Physical layer(10) converts ATM cell inputted to SB point in ATM network to bit stream. Then, ATM AAL3/4,5 layer(8) converts the bit stream to cell data of ATM and AAL3/4,5 format. The information of cell data such as ATM header, AAL type information, packet size etc. is stored in control memory(9), and packet data is stored in packet memory(7). Microprocessor(1) determines the type of data by the data stored in control memory(9), and outputs data stored in the packet memory(7) to LAN interface(5) or frame relay interface(6) according to the type of data. LAN interface(5) and frame relay interface(6) convert the received packet data to LAN data and frame relay data respectively, and transmit to R point.
Besides, microprocessor(1) control all the device and carry out the conversion of protocol. Memory(2) consists of ROM(Read Only Memory) and RAM(Random Access Memory). Device control circuit(3) comprises of device selection portion, and peripheral circuit(4) comprises of SIO(Serial Input Output), timer. Power supply(11) convert AC power to DC power which is necessary to the device.
The terminal adapter for BISDN according to the above prior art described in FIG. 1 is not applicable to various type of ATM cell. In connecting SB point to R point, it is applicable to only variable bit rate ATM cell, and not applicable to constant bit rate ATM cell.
Hence, there is a need for enhanced terminal adapter for BISDN which is applicable to the both of variable bit rate ATM cell and constant bit rate ATM cell for connecting SB point to R point.
Therefore, an object of the present invention is to provide a terminal adapter, which is applicable to the both of variable bit rate ATM cell and constant bit rate ATM cell for connecting SB point to R point.
In order to accomplish this object, the present invention provides a terminal adapter for BISDN comprising: ATM AAL3/4,5 layer converting a variable bit rate data to ATM cell; a plurality of constant bit rate interfaces converting a constant bit rate data to ATM cell respectively; physical layer converting physical layer data to ATM cell; and multiplexer/demultiplexer which determines priority and selects ATM cell among the both of variable bit rate ATM cell and constant bit rate ATM cell and outputs the selected ATM cells to the said physical layer according to the determined priority in case of transmitting data from R point to SB point, or determines the type of ATM cell and output variable bit rate ATM cell to the said ATM AAL3/4,5 layer, constant bit rate ATM cell to one of the said plurality of constant bit rate interfaces in case of transmitting data from SB point to R point.
In case of transmitting data from R point to SB point, the said multiplexer/demultiplexer according to the present invention operates as multiplexer. On the contrary, in case of transmitting data from SB point to R point, it operates as demultiplexer.
The said multiplexer/demultiplexer of terminal adapter according to the present invention comprises UTOPIA(Universal Test and Operation Physical Layer Interface for ATM) interface connecting the said multiplexer/demultiplexer to the said physical layer; the first FIFO receiving VBR cell from the said ATM AAL3/4,5 layer; VBR controller receiving VBR control signal from the said ATM AAL3/4,5 layer and controlling output of VBR cell from the said the first FIFO; the second FIFO(First In First Out) receiving CBR cell from the said constant bit rate interfaces; CBR controller receiving CBR control signals from the said constant bit rate interfaces and controlling output of CBR cell from the said the second FIFO; transmission priority determining block determining the transmission priority between CBR cell and VBR cell; and UTOPIA transmission controller transmitting CBR cell or VBR cell to UTOPIA interface in due sequence determined by the said transmission priority determining block.
The said multiplexer/demultiplexer of terminal adapter according to the present invention also comprises UTOPIA reception controller receiving ATM cell from the physical layer in case of transmitting date from SB point to R point; header storage resister storing VPI(Virtual Path Identifier) value and VCI(Virtual Channel Identifier) value of the received ATM cell; and cell transmission controller determining the type of ATM cell by the value stored in the header storage register and transmitting CBR cell to one of the said constant bit rate interfaces, VBR cell to the ATM AAL3/4,5 layer.